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DescriptionQ1006
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Q1006DesignQualcommASIC interview problem

Pair setup and hold multicycle constraints

TechniquesDesignSTATimingPairconstraints
DifficultyMedium
TopicTiming & STA
LanguageSystemVerilog
Format4 choices
01

Problem

A same-clock data path is intentionally allowed two destination cycles for setup. The design still requires data to be held relative to the original launch relationship. What is the usual paired multicycle intent for this two-cycle path?

02

Answer choices (4)