Hardware interview practice

Pair setup and hold multicycle constraints

MediumTiming & STASystemVerilog

A same-clock data path is intentionally allowed two destination cycles for setup. The design still requires data to be held relative to the original launch relationship. What is the usual paired multicycle intent for this two-cycle path?

Choose one

Answer choices

A. Apply only a setup false path because every multicycle path is functionally false.
B. Apply setup multicycle 2 and hold multicycle 2 to the same endpoints without checking edges.
C. Double the clock period globally and leave the path unconstrained.
D. Apply a setup multicycle of 2 and the corresponding hold multicycle of 1, then verify the tool-specific endpoints and edge report.

Continue practicing

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Answer choices

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