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DescriptionQ789

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Q789DesignQualcommASIC interview problem

Transfer Fast Events to a Slow Clock Exactly Once

TechniquesDesignCDCClocking

DifficultyHard

TopicClock and Reset Domains

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A 400 MHz source reports single-cycle events to an unrelated 80 MHz destination. Events must not be lost or duplicated; one event may remain outstanding while the round-trip acknowledgment is in progress. Implement a toggle-and-acknowledgment event bridge with source backpressure.

Module declarationSystemVerilog

module event_cdc(
 input logic clk_f,rst_f_n,event_valid, output logic event_ready,
 input logic clk_s,rst_s_n, output logic event_pulse_s
);
reset protocol: both resets assert together before either domain runs

Example input and output

Use this case to check your interpretation

Input

Case 1: Accept one 2.5 ns source pulse
Case 2: Keep request and returned acknowledgment different
Case 3: Issue two source events separated by a complete acknowledgment round trip

Output

Case 1: one 12.5 ns destination-cycle pulse eventually occurs despite the shorter source pulse
Case 2: event_ready stays zero and held event_valid is accepted only after event_ready returns high
Case 3: two distinct destination pulses occur in order

Explanation

The shown result follows by applying this rule: Only stable toggle states cross the domains, with a two-flop synchronizer in each direction and no combinational CDC path. The cases also demonstrate this requirement: Coordinated reset clears request, acknowledgment, synchronizer stages, and event_pulse_s; outputs from the first clean post-reset transaction count once, and one-sided reset while traffic is active is illegal.

Requirements (4)

In clk_f, toggle a request bit only on event_valid&&event_ready; event_ready is high exactly when the synchronized acknowledgment equals the current request toggle.
Pass the request through a two-flop clk_s synchronizer, compare it with the last acknowledged value, and emit one clk_s pulse when they differ.
After emitting the pulse, copy the received request value into the slow acknowledgment, synchronize that value back through two clk_f flops, and accept no second event before it returns.
Coordinated reset clears request, acknowledgment, synchronizer stages, and event_pulse_s; outputs from the first clean post-reset transaction count once, and one-sided reset while traffic is active is illegal.