1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ182

Q182DesignIntelASIC interview problem

Implement a four-phase CDC event handshake

TechniquesDesignCDC

DifficultyMedium

TopicClock and Reset Domains

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A one-cycle `src_event` in an unrelated source domain must produce exactly one destination pulse. Only one event may be outstanding; `src_ready` provides backpressure. Implement the request/acknowledge bridge.

Starting declarationSystemVerilog

source: src_clk,src_rst_n,src_event,src_ready
destination: dst_clk,dst_rst_n,dst_pulse
internal: source request level and destination acknowledge level
reset protocol: both resets assert for a flush; releases are locally synchronized

Example input and output

Use this case to check your interpretation

Input

Case 1: Accept one source event
Case 2: Present a second src_event while src_ready=0
Case 3: Wait until acknowledge returns and request and acknowledge are both low

Output

Case 1: exactly one destination pulse occurs even if request stays high for several destination cycles
Case 2: the event is not accepted and creates no additional destination pulse
Case 3: src_ready becomes 1 and the next event can be accepted

Explanation

The shown result follows by applying this rule: Use two-flop level synchronizers in both directions and edge detection only on the synchronized destination request. The cases also demonstrate this requirement: Coordinated reset clears request, acknowledge, pulse, and busy state; events during reset or while src_ready is low are not accepted.

Requirements (4)

Accept an event only when src_event&&src_ready, raise and hold a source request level, and keep src_ready low until the complete round trip finishes.
Synchronize request into the destination, generate exactly one dst_pulse on its low-to-high observation, and hold acknowledge high while request remains high.
Synchronize acknowledge to the source, lower request after high acknowledge, and lower acknowledge after the destination observes request low.
Coordinated reset clears request, acknowledge, pulse, and busy state; events during reset or while src_ready is low are not accepted.