Skip to the selected question
ASIC.FYI

ASIC Question Bank

1,000+ hardware interview questions
Question bank1050 results
  1. Easy
  2. Medium
  3. Medium
  4. Easy
  5. Easy
  6. Easy
  7. Easy
  8. Easy
  9. Easy
  10. Easy
  11. Medium
  12. Medium
  13. Hard
  14. Hard
  15. Medium
  16. Medium
  17. Medium
  18. Medium
  19. Medium
  20. Easy
  21. Medium
  22. Easy
  23. Hard
  24. Medium
  25. Hard
  26. Medium
  27. Hard
  28. Medium
  29. Easy
  30. Medium
  31. Medium
  32. Hard
  33. Hard
  34. Medium
  35. Hard
  36. Easy
  37. Medium
  38. Medium
  39. Medium
  40. Hard
  41. Medium
  42. Easy
  43. Medium
  44. Easy
  45. Medium
  46. Medium
  47. Medium
  48. Medium
  49. Medium
  50. Medium
DescriptionQ210
Q210DesignQualcommASIC interview problem

Separate related-clock timing from asynchronous CDC

TechniquesDesignCDCClocking
DifficultyEasy
TopicClock and Reset Domains
LanguageSystemVerilog
Format4 choices
01

Problem

Clock A and clock B are generated by one PLL with a fixed 2:1 ratio and documented phase. Clock C comes from an independent crystal oscillator. How should crossings be treated?

02

Answer choices (4)