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DescriptionQ1005
Q1005DesignQualcommASIC interview problem

Size a synchronizer from an MTBF target

TechniquesDesignCDCClocking
DifficultyMedium
TopicClock and Reset Domains
LanguageSystemVerilog
Format4 choices
01

Problem

A stable one-bit asynchronous level enters a 500 MHz destination domain. The library MTBF calculation shows that a two-stage synchronizer misses the product reliability target. The source toggle rate and destination clock cannot change. Which design decision is technically justified?

02

Answer choices (4)