DescriptionQ573
Q573DVASIC interview problem
Timing between start_item and finish_item
TechniquesUVMSequence arbitration and exclusivity
DifficultyEasy
TopicUVM Components
LanguageSystemVerilog
Format4 choices
01
Problem
What is the main problem with this sequence body?
Starting declarationSystemVerilog
start_item(req);
assert(req.randomize());
#100ns;
finish_item(req);02