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DescriptionQ185
Q185DVASIC interview problem

Sequencer locks and grabs

TechniquesUVMSequence arbitration and exclusivity
DifficultyHard
TopicUVM Components
LanguageSystemVerilog
Format4 choices
01

Problem

Sequence A locks a sequencer and then waits for an event that can be generated only after sequence B sends an item on that same sequencer. Why can the test deadlock?

02

Answer choices (4)