Hardware interview practice

Timing between start_item and finish_item

EasyUVM ComponentsSystemVerilog

What is the main problem with this sequence body?

Starting point

Question code

start_item(req);
assert(req.randomize());
#100ns;
finish_item(req);

Choose one

A. randomize is illegal after start_item
B. Consuming time after the grant and before finish_item holds sequencer access and can block other sequences; place the gap after finish_item returns, after the driver's item_done
C. finish_item must always be called in a forked process
D. A sequence item may not contain random fields

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