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DescriptionQ523
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Q523DesignGoogleASIC interview problem

Avoid multi-bit reconvergence errors

TechniquesDesignCDCReconvergenceMulti-bit
DifficultyMedium
TopicClock Domain Crossing
LanguageSystemVerilog
Format4 choices
01

Problem

A two-bit mode changes directly from 2'b01 to 2'b10 in the source domain. Each bit is passed through its own two-flop destination synchronizer. Why can destination logic still observe an invalid mode?

02

Answer choices (4)