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Hardware interview practice

Avoid multi-bit reconvergence errors

MediumClock Domain CrossingSystemVerilog

A two-bit mode changes directly from 2'b01 to 2'b10 in the source domain. Each bit is passed through its own two-flop destination synchronizer. Why can destination logic still observe an invalid mode?

Choose one

Answer choices

  1. A. Two-flop synchronizers are safe only when the source and destination clocks have the same frequency.
  2. B. The two bits can settle on different destination cycles, so independently synchronized bits may temporarily form 00 or 11.
  3. C. The source transition is illegal because a two-bit register cannot change both bits on one edge.
  4. D. The second synchronizer stage intentionally inverts one bit to detect metastability.
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