1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ038

Q038DesignDVASIC interview problem

Generate and synchronize a Gray-code counter

TechniquesGray codeCounterCDCSingle-bit transitions

DifficultyMedium

TopicClock Domain Crossing

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design a parameterized counter whose exported Gray code changes by one bit per source increment, then synchronize that Gray value into a destination clock domain.

Example input and output

Use this case to check your interpretation

Input

WIDTH=3; enabled source binary counts=[0,1,2,3]

Output

registered Gray values=[000,001,011,010]; each appears in destination after two destination edges

Explanation

Each source increment changes one Gray bit, while the marked two-flop chain still handles metastability before destination use.

Requirements (4)

Increment the binary source count by at most one on each enabled source edge.
Register Gray code derived from the next binary value.
Use a two-flop destination synchronizer for every Gray bit and mark the chain for CDC tools.
Explain that Gray coding limits transition ambiguity but does not remove metastability or replace synchronization.