1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ491

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Q491DesignAMDASIC interview problem

Transfer spaced events with a toggle synchronizer

TechniquesDesignCDCClocking

DifficultyHard

TopicClock and Reset Domains

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A 500 MHz source sends one-cycle events to a 100 MHz destination. Clocks have rising edges at integer multiples of 2 ns and 10 ns. Every legal event is sampled at least 1 ns before a destination edge, and legal events are at least 40 ns apart. Implement a toggle-based event crossing for the stated spacing contract.

Starting declarationSystemVerilog

source: src_clk,src_rst_n,src_event
destination: dst_clk,dst_rst_n,dst_pulse
internal: source toggle; sync1,sync2,sync2_d in destination
dst_pulse is combinational sync2 XOR sync2_d
reset protocol: both domains reset together; no event during release

Example input and output

Use this case to check your interpretation

Input

Case 1: An event sampled at source time 8 ns
Case 2: Scenario: Events sampled at 8 ns and 48 ns produce pulses at 20 ns and 60 ns, respectively.
Case 3: A coordinated reset with no event

Output

Case 1: Is captured by destination stage one at 10 ns and produces one dst_pulse at 20 ns.
Case 2: Expected behavior: Events sampled at 8 ns and 48 ns produce pulses at 20 ns and 60 ns, respectively.
Case 3: Leaves the toggle, both synchronizer stages, delayed copy, and dst_pulse at zero.

Explanation

The shown result follows by applying this rule: Use one source-domain toggle register and a two-stage destination synchronizer marked with the CDC flow's synchronizer property. The cases also demonstrate this requirement: Document that closer events violate this no-backpressure contract; use a handshake or counter instead if arbitrary bursts must be lossless.

Requirements (4)

Toggle one source bit on every legal src_event and otherwise hold it; coordinated reset clears the toggle.
Register the toggle through sync1 and sync2, register sync2_d as the prior sync2 value, and drive dst_pulse combinationally as sync2 XOR sync2_d. Do not add another registered output stage.
Under the 40 ns minimum spacing and ideal RTL sampling assumptions, produce exactly one destination pulse per source event and no spontaneous pulse.
Document that closer events violate this no-backpressure contract; use a handshake or counter instead if arbitrary bursts must be lossless.