DescriptionQ170
Q170DVASIC interview problem
Vacuity
TechniquesSystemVerilogAdvanced assertions
DifficultyMedium
TopicTemporal Checks
LanguageSystemVerilog
Format4 choices
01
Problem
An assertion has passed for the entire test, but req was never asserted. Which addition most directly exposes this vacuous-success hole?
Starting declarationSystemVerilog
assert property (@(posedge clk) req |-> ##[1:3] ack);02
