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Vacuity

MediumTemporal ChecksSystemVerilog

An assertion has passed for the entire test, but req was never asserted. Which addition most directly exposes this vacuous-success hole?

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Question code

assert property (@(posedge clk) req |-> ##[1:3] ack);
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Answer choices

  1. A. Replace |-> with logical ==
  2. B. Add cover property (@(posedge clk) req) and require it to hit
  3. C. Add disable iff (req)
  4. D. Change ack to $isunknown(ack)
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