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DescriptionQ040
Q040DVDesignASIC interview problem

Sequence local variables

TechniquesSystemVerilogAdvanced assertions
DifficultyHard
TopicTemporal Checks
LanguageSystemVerilog
Format4 choices
01

Problem

What does local variable t accomplish, and what does this sequence still not guarantee?

Type declarationSystemVerilog
typedef logic [7:0] tag_t;
tag_t req_tag, rsp_tag;

sequence tagged_response;
  tag_t t;
  (req, t = req_tag) ##[1:3] (ack && rsp_tag == t);
endsequence
02

Answer choices (4)