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DescriptionQ707
Q707DVDesignASIC interview problem

$past and nonblocking assignment (NBA) sampling

TechniquesSystemVerilogAdvanced assertions
DifficultyHard
TopicTemporal Checks
LanguageSystemVerilog
Format4 choices
01

Problem

After the first usable history sample, how should this property behave when d is known and stable around each posedge and q has no other drivers?

Starting declarationSystemVerilog
always_ff @(posedge clk) q <= d;
assert property (@(posedge clk) q == $past(d));
02

Answer choices (4)