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Models · transactions · scalable regressions

Verification Infrastructure Engineer Interview Questions

Design the reusable models, scoreboards, transaction stores, concurrency controls, diagnostics, register abstractions, and regression utilities that keep verification environments scalable.

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Difficulty
Showing 38 of 38All questions visible
  1. Q148Verification UtilitiesDirect Programming Interface (DPI) 4-state data mappingSystemVerilog · DPI/C interoperabilityMedium
  2. Q209Verification UtilitiesVirtual interfacesSystemVerilog · Interfaces and timingEasy
  3. Q235Verification UtilitiesClocking blocksSystemVerilog · Interfaces and timingEasy
  4. Q279Verification UtilitiesInterface modportsSystemVerilog · Interfaces and timingEasy
  5. Q173Verification UtilitiesDetect a deadlock in a wait graphGraph · DeadlockMedium
  6. Q185Verification UtilitiesRegress cross-transaction histogram leakageDV · RegressionHard
  7. Q008UVM Componentsuvm_object versus uvm_componentUVM · Class roles and constructionEasy
  8. Q252UVM ComponentsBuild and connect phasesUVM · Phase lifecycle and orderingEasy
  9. Q296UVM ComponentsPhase objectionsUVM · Objections and drain timeEasy
  10. Q245UVM ComponentsFactory type overridesUVM · Factory override resolutionEasy
  11. Q044UVM ComponentsConfig_db virtual interface distributionUVM · Configuration scoping and precedenceEasy
  12. Q263UVM ComponentsSequencer-driver connectionUVM · Pull protocol handshakeEasy
  13. Q077UVM ComponentsGet_next_item and item_doneUVM · Pull protocol handshakeEasy
  14. Q170UVM ComponentsAnalysis port semanticsUVM · Analysis distributionEasy
  15. Q053Reference ModelsOut-of-order scoreboard matchingUVM · Checking architectureMedium
  16. Q297UVM ComponentsDrive a ready/valid interface correctlyUVM · DriverMedium
  17. Q1102UVM ComponentsDrive a multi-beat ready/valid transactionUVM · DriverMediumP
  18. Q910UVM ComponentsBuild a reset-responsive nonblocking driverUVM · DriverHardP
  19. Q760UVM ComponentsMonitor a ready/valid interfaceUVM · MonitorMediumP
  20. Q1003UVM ComponentsReassemble interleaved transactions by IDUVM · MonitorHardP
  21. Q792Reference ModelsMatch transactions in strict orderUVM · ScoreboardMediumP
  22. Q442Functional CoverageCover handshakes and backpressureUVM · CoverageMediumP
  23. Q1033UVM ComponentsStart_item and finish_itemUVM · Sequence arbitration and exclusivityEasyP
  24. Q192UVM ComponentsSequencer locks and grabsUVM · Sequence arbitration and exclusivityMedium
  25. Q1023UVM ComponentsVirtual sequencersUVM · Virtual sequence coordinationEasyP
  26. Q155UVM ComponentsSequence response queue depthUVM · Response queue managementEasy
  27. Q805UVM ComponentsBlocking and nonblocking transaction-level modelingUVM · TLM interfacesEasyP
  28. Q853UVM ComponentsTransaction-level modeling port, export, and imp rolesUVM · TLM interfacesEasyP
  29. Q269UVM ComponentsAnalysis FIFO backpressureUVM · TLM interfacesEasy
  30. Q778UVM ComponentsConfiguration object ownershipUVM · Integration and end-of-testMediumP
  31. Q183UVM ComponentsCheck_phase and final checkingUVM · Integration and end-of-testEasy
  32. Q165UVM ComponentsEnd run phase with a forever monitorUVM · ObjectionsMedium
  33. Q706UVM ComponentsConfigure two reusable agents in one environmentUVM · Agent configurationMediumP
  34. Q566UVM ComponentsCoordinate two sequencers with a virtual sequenceUVM · Virtual sequenceHardP
  35. Q829UVM ComponentsTurn an APB3 agent into reusable verification IPAPB3 · UVMHardP
  36. Q602UVMConnect a UVM monitor to a scoreboardDV · UVMMediumP
  37. Q026Reference ModelsRetire out-of-order completions in orderPython · RetirementHard
  38. Q033Reference ModelsMatch out-of-order packets by IDScoreboard · Out-of-orderMedium

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  • Easy18
  • Medium14
  • Hard6

Related learning

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These are the guides most often linked by questions in this collection.

  1. 01UVM Factory and StimulusReview factory overrides, configuration, sequences, sequencers, and drivers.13
  2. 02UVM Checking and DebugReview monitors, TLM, scoreboards, reports, response matching, and register models.11
  3. 03UVM Architecture and LifecycleReview component roles, agents, phases, objections, domains, and end of test.3
  4. 04Ordering and Memory ConsistencyReview legal reordering, global visibility, identities, dependencies, and consistency evidence.2
  5. 05SystemVerilogReview the language mechanisms used to express RTL, verification intent, and testbench behavior.2
  6. 06Cancellation and Concurrency DebugReview process control, timeouts, cleanup, deadlock, and progress debugging.1
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