TLM, scoreboards, reports, and UVM RAL interview questions

Question 1

How does an analysis port differ from put or get TLM interfaces?

Accepted Answer

An analysis port broadcasts a transaction through a zero-time write() function to every connected subscriber. Put and get interfaces model directed transfer and may be blocking or nonblocking. A monitor commonly broadcasts observations to coverage, a predictor, and one or more scoreboards. Subscribers must not consume time inside write() or modify the shared transaction. Clone it or use a uvm_tlm_analysis_fifo when deferred processing is required. The sequencer-driver path uses the specialized seq_item_port and seq_item_export pull interface, not an ordinary uvm_tlm_put_port or uvm_tlm_get_port. Watch for: Calling analysis connections strictly one-to-many and put/get strictly one-to-one oversimplifies legal TLM topology. Their interface semantics are the important distinction.

Question 2

Trace one transaction from a sequence to a scoreboard.

Accepted Answer

The sequence creates intent, the driver realizes it on pins, the DUT transforms it, and the monitor reconstructs a new observed transaction for the checking path. A leaf sequence sends a request through its sequencer to the driver. The driver applies the protocol to a virtual interface. The monitor samples signal activity independently and publishes a fresh actual transaction. It should not reuse the request handle. A predictor or reference model creates expected behavior from the appropriate inputs. The scoreboard aligns expected and actual streams, then compares them. Watch for: Comparing the original request directly with a DUT output is valid only when the DUT contract is truly identity and timing has been accounted for.

Question 3

What is the difference between UVM_ERROR and UVM_FATAL?

Accepted Answer

UVM_ERROR reports a recoverable test failure and normally lets simulation continue. UVM_FATAL reports an unusable testbench state and normally exits immediately. Use an error for a data mismatch or protocol violation when more evidence can still be collected. Use a fatal for missing required configuration, an incompatible topology, or another condition that makes later results meaningless. Severity, action, and quit-count policy can be configured or changed by a report catcher, but overrides should preserve a clear regression contract. Watch for: A fatal is not merely a larger error count. Its default action includes simulation exit.

Question 4

A UVM test hangs. What do you check first?

Accepted Answer

Start with phase control, then trace the sequencer-driver contract, topology, blocked waits, and finally clock or reset progress. Run with +UVM_OBJECTION_TRACE and +UVM_PHASE_TRACE. Identify the active phase, the source of every remaining objection, and whether another phase domain is still running. Check start_item/finish_item against get_next_item/item_done, confirm the sequence started on the intended sequencer, and verify the port-export connection and parameter types. Inspect waits, semaphores, events, response queues, clocks, and reset release. Add bounded timeouts around scenario-level waits so deadlock becomes a diagnostic failure. Watch for: A driver forever loop is normal and does not keep a phase alive by itself. An objection, blocked phase callback, or unsynchronized run-time domain does.

Question 5

What does the UVM Register Abstraction Layer provide?

Accepted Answer

RAL gives tests a named model of registers, fields, maps, access policies, desired values, and mirrored values, independent of the bus used to reach the DUT. A register map and adapter translate a model operation into protocol-specific bus items for frontdoor access. Backdoor access reaches the HDL path directly when configured. The model mirror stays trustworthy only when prediction is configured. Use auto-predict for simple frontdoor flows or an explicit predictor connected to the bus monitor. RAL improves portability and supplies standard access sequences and optional coverage, but it does not replace protocol checking or a correct predictor. Watch for: Frontdoor-versus-backdoor comparison is not automatic. The test must perform a mirror, read, or check operation with the intended prediction policy.

Interface	Communication	Typical use
analysis	Broadcast `write()`, no time	Monitor fan-out
put/get	Directed, blocking or nonblocking	Producer-consumer transport
`seq_item`	Arbitrated request/completion	Sequencer-driver

Severity	Default intent	Example
`UVM_ERROR`	Record failure and continue	Scoreboard mismatch
`UVM_FATAL`	Report and exit	Required virtual interface missing

Questions for Checking + debug

UVM TLM and checking paths Separate actual from expected.

Observation is a broadcast; checking is a comparison

Reason it through

Reason it through

UVM Reports, debug, and RAL Close the loop with evidence.

RAL frontdoor and prediction path

Reason it through

Reason it through

Reason it through

Checking + debugTLM, scoreboards, reports, and UVM RALInterview guide

UVM TLM and checking paths Separate actual from expected.

Observation is a broadcast; checking is a comparison

How does an analysis port differ from put or get TLM interfaces?+

Reason it through

Trace one transaction from a sequence to a scoreboard.+

Reason it through

UVM Reports, debug, and RAL Close the loop with evidence.

RAL frontdoor and prediction path

What is the difference between UVM_ERROR and UVM_FATAL?+

Reason it through

A UVM test hangs. What do you check first?+

Reason it through

What does the UVM Register Abstraction Layer provide?+

Reason it through