Part 3 · Budgets and handoff

Close quantitative budgets and hand off the evidence

Connect bandwidth, latency, buffering, outstanding work, implementation cost, and PPA, then deliver the decisions and proof obligations downstream.

Learn to expose missing assumptions early, budget throughput and buffering with units, choose structures deliberately, and preserve bidirectional traceability through RTL and verification.

Updated July 20262 connected chaptersInteractive labs + worked examples

Budgets before optimism

Connect bandwidth, latency, buffering, and PPA.

Peak width times frequency is only a ceiling. A credible microarchitecture closes sustained service, outstanding work, burst granularity, arbitration, and implementation margin together.

Bytes / beat32 B256 ÷ 8

Raw peak16 GB/s32 B × 500 MHz

Payload service efficiency87.5%14 GB/s accepted payload ÷ raw peak

Required utilization75%12 ÷ 16

Arrival rate0.75 beat/cycletarget ÷ raw beat bandwidth

Fixed-latency window60 beatsarrival rate × round-trip cycles

Minimum whole bursts4ceil(60 ÷ 16)

Zero-service stall backlog60 beats1,920 B if the source cannot be backpressured for 80 cycles

The rate assumptions are physically consistent.

Sustained payload service is below the raw peak and above the target. The latency window sizes accepted in-flight context; the stall backlog separately assumes zero service while an upstream source continues and cannot be backpressured.

Illustrative normalized estimates

Compare architecture hypotheses, not colors.

Replace these early estimates with model, synthesis, and power evidence before selection.

more throughputmore implementation cost

Evidence before RTL

Hand off decisions, not just diagrams.

A microarchitecture is ready when downstream teams can implement, verify, constrain, program, and review it without recovering hidden intent from meetings.

Handoff completeness0 / 6

RTL

Implementable structure

Block boundaries, state machines, widths, pipeline stages, interface contracts, reset values, and illegal-state behavior.

Verification

Observable proof plan

Requirement IDs, scenarios, reference behavior, assertions, coverage, error injection, counters, and closure criteria.

Firmware

Stable software contract

Implementation

Physical feasibility

Clock and power domains, memories, multicycle intent, floorplan pressure, target corners, activity assumptions, and PPA budgets.

Reasoning checkpoints

Questions worth answering without notes.

Each answer states the mechanism first, then the consequence.

01How do you know whether to add buffering or improve service rate?

Buffering absorbs finite bursts and latency variation, but it cannot repair a sustained arrival rate that exceeds sustained service rate. First compare long-term rates, then size finite storage from the maximum permitted burst and response-latency envelope with explicit backpressure assumptions.

02What belongs in a microarchitecture handoff?

Include requirements traceability, block and clock/reset/power boundaries, interface contracts, state ownership, ordering and error rules, cycle-level scenarios, performance and storage calculations, configuration and status behavior, observability hooks, unresolved risks, and a verification strategy for every important invariant.

Keep practicing

Move from recognition to explanation.

These links open the existing practice bank without publishing protected solutions on this guide.

Size a FIFO under unstable rateSeparate finite burst absorption from sustained overload.Budget an SoC from a workloadTranslate traffic, latency, and power intent into measurable architecture budgets.Trade sharing against throughputDecide when a shared engine meets the service contract and when parallel hardware is required.

Continue the system

Connect the adjacent layer.

Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Safe boundaries across time and voltageClock, Reset, CDC and PowerOperate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.RTL intent to signoff marginSynthesis and Timing ClosureAutopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.