1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ499

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Q499DVNVIDIAASIC interview problem

Assert set-dominant fault retention

TechniquesDVSVAFormalAssertSet-Dominant

DifficultyMedium

TopicAssertions and Formal

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A sticky fault bit has synchronous active-low reset, a set input, and a clear input; set must win when both are one. Write SystemVerilog assertions that fully check the next-cycle behavior.

Starting declarationSystemVerilog

input logic clk, rst_n;
input logic set, clear, sticky;

Example input and output

Use this case to check your interpretation

Input

At C0, sticky = 0 and both set and clear are 1.

Output

sticky is required to be 1 at C1.

Explanation

The specified next-state priority is set-dominant when set and clear are asserted together.

Requirements (4)

On a sampled cycle with rst_n=0, sticky must be zero immediately after that edge.
If rst_n, set, and clear are all one, sticky must be one after that edge.
If rst_n=1, set=0, and clear=1, sticky must be zero after that edge.
If rst_n=1 and set=clear=0, sticky must retain its previous value after that edge.