1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ166

Q166DVDesignIntelASIC interview problem

Prove clock-gating entry and wake safety

TechniquesDVDesignFormalClocking

DifficultyHard

TopicAssertions and Formal

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A CPU block gates its local clock after all accepted work completes and must wake within three parent-clock cycles of wake_req. Write the formal assumptions, assertions, and covers for the gate controller.

Starting declarationSystemVerilog

parent_clk, reset_n
accepted_work_count
idle, gate_closed
wake_req
local_clk_running

Example input and output

Use this case to check your interpretation

Input

Case 1: Raise gate_closed while accepted_work_count=1
Case 2: Assert wake_req while gated
Case 3: Assert reset while gated

Output

Case 1: the entry-safety assertion fails
Case 2: local_clk_running becomes true within cycles 1–3
Case 3: gate_closed=0 and local_clk_running=1 by the specified reset edge

Explanation

The shown result follows by applying this rule: Entry safety, state stability, bounded wake, and reset are separate properties. The cases also demonstrate this requirement: Assert reset forces the defined open-gate state; cover normal gate, wake, reset while gated, and wake with the final completion.

Requirements (4)

Assert gate_closed may rise only when accepted_work_count == 0 and idle is true.
Assert functional state remains stable while gated except the specified wake/reset logic.
Assume parent_clk continues; assert wake_req opens the gate and local_clk_running becomes true within three parent-clock cycles.
Assert reset forces the defined open-gate state; cover normal gate, wake, reset while gated, and wake with the final completion.