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Assert set-dominant fault retention

MediumAssertions and FormalSystemVerilog

A sticky fault bit has synchronous active-low reset, a set input, and a clear input; set must win when both are one. Write SystemVerilog assertions that fully check the next-cycle behavior.

Starting point

Question code

input logic clk, rst_n;
input logic set, clear, sticky;
Reviewed example

Work through one case

Input
At C0, sticky = 0 and both set and clear are 1.
Expected output
sticky is required to be 1 at C1.

The specified next-state priority is set-dominant when set and clear are asserted together.

What to cover

Requirements

  1. On a sampled cycle with rst_n=0, sticky must be zero immediately after that edge.
  2. If rst_n, set, and clear are all one, sticky must be one after that edge.
  3. If rst_n=1, set=0, and clear=1, sticky must be zero after that edge.
  4. If rst_n=1 and set=clear=0, sticky must retain its previous value after that edge.
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