1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ694

Page ↗

Q694DesignBroadcomASIC interview problem

Four-bit JTAG instruction register

TechniquesDFT & Physical DesignPhysical Design / DFTfour-bit jtag instruction register

DifficultyMedium

TopicDFT & Physical Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A small TAP instruction register supports CAPTURE-IR, SHIFT-IR, and UPDATE-IR controls from an existing TAP controller. Write synthesizable SystemVerilog for the instruction register and decoder.

Starting declarationSystemVerilog

input logic tck, trst_n, capture_ir, shift_ir, update_ir, tdi;
output logic tdo;
output logic extest, idcode, bypass;
// opcodes: EXTEST=0000, IDCODE=0001, others=BYPASS

Example input and output

Use this case to check your interpretation

Input

Assert trst_n=0.

Output

active_ir=4'b0001, idcode=1, extest=0, and bypass=0.

Explanation

Asynchronous reset loads the IDCODE opcode into the active instruction register, and the one-hot decoder selects only idcode.

Requirements (4)

Use separate four-bit shift and active instruction registers; asynchronous active-low reset sets both registers to IDCODE.
On a TCK rising edge, CAPTURE-IR has priority and loads shift register 4'b0001; otherwise SHIFT-IR shifts toward bit0 with tdi entering bit3.
On UPDATE-IR, copy the shift register to the active instruction; if controls overlap, capture/shift updates the shift register and update copies its pre-edge value.
Drive tdo from shift[0] and decode exactly one of extest, idcode, or bypass from the active instruction.