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Four-bit JTAG instruction register

MediumDFT & Physical DesignSystemVerilog

A small TAP instruction register supports CAPTURE-IR, SHIFT-IR, and UPDATE-IR controls from an existing TAP controller. Write synthesizable SystemVerilog for the instruction register and decoder.

Starting point

Question code

input logic tck, trst_n, capture_ir, shift_ir, update_ir, tdi;
output logic tdo;
output logic extest, idcode, bypass;
// opcodes: EXTEST=0000, IDCODE=0001, others=BYPASS
Reviewed example

Work through one case

Input
Assert trst_n=0.
Expected output
active_ir=4'b0001, idcode=1, extest=0, and bypass=0.

Asynchronous reset loads the IDCODE opcode into the active instruction register, and the one-hot decoder selects only idcode.

What to cover

Requirements

  1. Use separate four-bit shift and active instruction registers; asynchronous active-low reset sets both registers to IDCODE.
  2. On a TCK rising edge, CAPTURE-IR has priority and loads shift register 4'b0001; otherwise SHIFT-IR shifts toward bit0 with tdi entering bit3.
  3. On UPDATE-IR, copy the shift register to the active instruction; if controls overlap, capture/shift updates the shift register and update copies its pre-edge value.
  4. Drive tdo from shift[0] and decode exactly one of extest, idcode, or bypass from the active instruction.
Continue practicing
DFT & Physical DesignSummarize one 32-bit scan-unload mismatch