1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ709

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Q709DesignMicronASIC interview problem

Summarize one 32-bit scan-unload mismatch

TechniquesDFT & Physical DesignPhysical Design / DFTsummarize one 32-bit scan-unload mismatch

DifficultyEasy

TopicDFT & Physical Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A scan diagnostic compares one expected unload word against the observed word and needs both a count and the first failing chain position. Implement the combinational mismatch summarizer.

Starting declarationSystemVerilog

input logic [31:0] expected, observed;
output logic mismatch;
output logic [4:0] first_index;
output logic [5:0] mismatch_count;

Example input and output

Use this case to check your interpretation

Input

expected=32'h0000_0000, observed=32'h0000_0028.

Output

mismatch=1, first_index=3, mismatch_count=2.

Explanation

The XOR difference mask has bits 3 and 5 set, so there are two mismatches and bit 3 is the lowest failing position.

Requirements (4)

Inputs contain only known bits. Define difference bit i as expected[i] XOR observed[i].
mismatch is 1 if at least one difference bit is set, and mismatch_count is the exact population count from 0 through 32.
When mismatch=1, first_index is the lowest-numbered differing bit; when mismatch=0, first_index is 0.
Use complete combinational RTL with a loop whose bounds are constant and synthesizable.