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DescriptionQ124
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Q124DesignQualcommASIC interview problem

Release reset safely in two clock domains

TechniquesCDC & RDCCDC / RDCrelease reset safely in two clock domains
DifficultyEasy
TopicCDC & RDC
LanguageSystemVerilog
Format4 choices
01

Problem

One active-low reset pin asynchronously resets logic in two unrelated clock domains. Which release strategy best avoids recovery/removal problems in each domain?

02

Answer choices (4)