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DescriptionQ416
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Q416DesignAppleASIC interview problem

Capture a held multi-bit power-state value across clocks

TechniquesCDC & RDCCDC / RDCcapture a held multi-bit power-state value across clocks
DifficultyEasy
TopicCDC & RDC
LanguageSystemVerilog
Format4 choices
01

Problem

A source clock domain changes a four-bit power-state value, asserts request, and promises to hold the value until an acknowledgement returns from the destination. Which destination-side scheme transfers one coherent value without synchronizing the four data bits independently?

02

Answer choices (4)