DescriptionQ1008
Q1008DesignGoogleASIC interview problem
Apply clock skew consistently
TechniquesTimingSTAClock skewSetup and hold
DifficultyEasy
TopicTiming
LanguageSystemVerilog
Format4 choices
01
Problem
Positive skew is defined as the capture clock arriving later than the launch clock on a same-clock path. How does increasing positive skew affect setup and hold slack, all else equal?
02