1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ554

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Q554DesignMetaASIC interview problem

Input-delay constraints from an external device

TechniquesTimingSTASDCI/O constraints

DifficultyMedium

TopicTiming

LanguageSystemVerilog

Requirements4 checkpoints

Problem

An external transmitter launches data on board_clk. Its clock-to-output range and board data delay are known; clock-board delay is the reference zero. Derive set_input_delay minimum and maximum values for each input group.

Starting declarationSystemVerilog

input_delay_min = tco_min + board_data_min
input_delay_max = tco_max + board_data_max

A = ( 0.4, 1.2, 0.20, 0.30) ns
B = ( 0.1, 0.8, 0.10, 0.20) ns
C = (-0.1, 0.5, 0.05, 0.15) ns
// tuple order: tco_min,tco_max,board_min,board_max

Example input and output

Use this case to check your interpretation

Input

Group C: tco_min=-0.10 ns, board_min=0.05 ns; tco_max=0.50 ns, board_max=0.15 ns

Output

set_input_delay -min -0.05 ns; set_input_delay -max 0.65 ns

Explanation

A negative minimum is valid here because the earliest data transition precedes the chosen external-clock reference at the chip boundary.

Requirements (4)

Use nanoseconds and preserve a negative minimum when the arithmetic produces one.
Apply both -min and -max relative to the same board_clk reference.
Do not add internal chip delays; STA accounts for those after the input port.
Show the derived values and corresponding SDC commands for groups A, B, and C.