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Hardware interview practice

Apply clock skew consistently

EasyTimingSystemVerilog

Positive skew is defined as the capture clock arriving later than the launch clock on a same-clock path. How does increasing positive skew affect setup and hold slack, all else equal?

Choose one

Answer choices

  1. A. It changes neither check because STA removes all clock arrival differences.
  2. B. It improves both setup and hold slack because the capture register always receives more time.
  3. C. It improves setup slack but reduces hold slack.
  4. D. It reduces setup slack but improves hold slack.
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