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DescriptionQ070
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Q070DesignGoogleASIC interview problem

Choose arithmetic shift behavior

TechniquesDesignSystemVerilogSigned arithmeticShift
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Format4 choices
01

Problem

`x` is declared `logic signed [7:0]` and contains `8'hF0`, which represents -16 in two's complement. What eight-bit result does `x >>> 2` produce?

02

Answer choices (4)