Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Choose arithmetic shift behavior

Hardware interview practice

Choose arithmetic shift behavior

EasyRTL DesignSystemVerilog

`x` is declared `logic signed [7:0]` and contains `8'hF0`, which represents -16 in two's complement. What eight-bit result does `x >>> 2` produce?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. 8'hF8, because shifting right by two changes only one sign-extension bit.
  2. B. 8'h3C, because every right shift fills the two high bits with zeros.
  3. C. 8'hC0, because the two low bits rotate into the high positions.
  4. D. 8'hFC, because arithmetic right shift replicates the sign bit and -16 divided by four is -4.
Continue practicing

Related questions

Reference ModelsVerify a longest rising-trend accelerator→RTL ArithmeticInterpret one mixed-sign addition explicitly→
asic.fyi · Learn silicon end to end.info@asic.fyi