DescriptionQ234
Q234DesignASIC interview problem
Interpret one mixed-sign addition explicitly
TechniquesDesignSystemVerilogSigned arithmeticExpression sizing
DifficultyMedium
TopicRTL Arithmetic
LanguageSystemVerilog
Format4 choices
01
Problem
For the shown 8-bit operands a = -2 and b = 3, which expression explicitly interprets both bit patterns as signed and produces the intended result 1?
Starting declarationSystemVerilog
logic signed [7:0] a = -8'sd2;
logic [7:0] b = 8'd3;
logic signed [8:0] sum;02
