DescriptionQ444
Q444DesignMetaASIC interview problem
Effect of positive capture skew
TechniquesDesignSTAClock skewSetupHold
DifficultyEasy
TopicStatic Timing Analysis
LanguageSystemVerilog
Format4 choices
01
Problem
For one register path, the capture clock arrives 60 ps later than the launch clock. Treat this as positive capture skew and leave all data delays unchanged. How does that skew affect timing margin?
02