Hardware interview practice

Effect of positive capture skew

EasyStatic Timing AnalysisSystemVerilog

For one register path, the capture clock arrives 60 ps later than the launch clock. Treat this as positive capture skew and leave all data delays unchanged. How does that skew affect timing margin?

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Answer choices

A. It has no effect because only the difference in data delays matters.
B. It reduces setup margin and improves hold margin.
C. It improves both setup and hold margin by 60 ps.
D. It improves setup margin and reduces hold margin.

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