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DescriptionQ1035
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Q1035DesignGoogleASIC interview problem

Know which violation frequency can fix

TechniquesDesignSTAHoldClock period
DifficultyEasy
TopicStatic Timing Analysis
LanguageSystemVerilog
Format4 choices
01

Problem

A same-clock register path has positive setup slack but -40 ps hold slack. No generated or opposite-edge clock is involved. What happens if the clock period is doubled?

02

Answer choices (4)