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Hardware interview practice

Know which violation frequency can fix

EasyStatic Timing AnalysisSystemVerilog

A same-clock register path has positive setup slack but -40 ps hold slack. No generated or opposite-edge clock is involved. What happens if the clock period is doubled?

Choose one

Answer choices

  1. A. The hold violation remains; same-edge hold timing does not gain a full clock period when frequency is reduced.
  2. B. Both setup and hold checks are disabled automatically below half the original frequency.
  3. C. The hold slack improves by one original clock period, so the violation disappears.
  4. D. The setup slack becomes negative because a longer period tightens the setup requirement.
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