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DescriptionQ513
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Q513DVDesignAMDASIC interview problem

Debug an X after reset release

TechniquesDVDesignResetFSM
DifficultyMedium
TopicDesign Verification
LanguageSystemVerilog
Format4 choices
01

Problem

RTL simulation passes, but gate simulation shows X on an FSM for two cycles after asynchronous reset releases. What is the strongest first response?

02

Answer choices (4)