Hardware interview practice
Debug an X after reset release
RTL simulation passes, but gate simulation shows X on an FSM for two cycles after asynchronous reset releases. What is the strongest first response?
Choose one
Answer choices
- A. Disable every timing check because RTL simulation passed.
- B. Assume all gate-level X values are simulator pessimism.
- C. Trace the first X and check unreset state, reset-domain crossing, recovery/removal, and power-intent initialization before masking it.
- D. Force the FSM state from the testbench so downstream checks can continue.