1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ084

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Q084DVNVIDIAASIC interview problem

Scoreboard burst-to-single conversion

TechniquesDVUVMScoreboardProtocolBackpressure

DifficultyHard

TopicVerification

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design a predictor and scoreboard for bursts of 1 to 16 words that become single-beat outputs at base_addr+4*i. Up to four bursts may be queued, and different IDs may interleave while each ID remains ordered.

Starting declarationSystemVerilog

// input burst: {base_addr,len,data[],burst_id}, valid/ready
// output beat: {addr,data,last,burst_id}, valid/ready

Example input and output

Use this case to check your interpretation

Input

Accepted burst id=2, base=0x100, len=3, data={A,B,C}

Output

Expected beats (0x100,A,not last), (0x104,B,not last), (0x108,C,last)

Explanation

The predictor expands one command into an ordered queue keyed by ID.

Requirements (4)

Expand only accepted input bursts and prevent ID reuse while that ID has expected beats.
Compare only accepted output handshakes.
Permit cross-ID interleaving but preserve order within each ID and exact last marking.
Check output stability under backpressure and flush every expectation on reset.