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Hardware interview practice

Scoreboard burst-to-single conversion

HardVerificationSystemVerilog

Design a predictor and scoreboard for bursts of 1 to 16 words that become single-beat outputs at base_addr+4*i. Up to four bursts may be queued, and different IDs may interleave while each ID remains ordered.

Starting point

Question code

// input burst: {base_addr,len,data[],burst_id}, valid/ready
// output beat: {addr,data,last,burst_id}, valid/ready
Reviewed example

Work through one case

Input
Accepted burst id=2, base=0x100, len=3, data={A,B,C}
Expected output
Expected beats (0x100,A,not last), (0x104,B,not last), (0x108,C,last)

The predictor expands one command into an ordered queue keyed by ID.

What to cover

Requirements

  1. Expand only accepted input bursts and prevent ID reuse while that ID has expected beats.
  2. Compare only accepted output handshakes.
  3. Permit cross-ID interleaving but preserve order within each ID and exact last marking.
  4. Check output stability under backpressure and flush every expectation on reset.
Continue practicing
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