1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ261

Q261DVNVIDIAASIC interview problem

Build a LIFO scoreboard

TechniquesDVSystemVerilogScoreboardStack

DifficultyEasy

TopicVerification

LanguageSystemVerilog

Requirements4 checkpoints

Model and check a depth-8, 16-bit stack, including simultaneous push/pop, overflow, underflow, and reset behavior.

Starting declarationSystemVerilog

// Sample after each rising edge:
{rst_n, push, pop, wdata, rdata, overflow, underflow}

Use this case to check your interpretation

Input

Model contains [A,B] with B on top; push=C and pop=1 in the same cycle

Output

rdata=B, no error, model becomes [A,C]

Explanation

The old top is returned before the simultaneous push replaces it.

Use a depth-8 reference stack and clear it on reset.
On a nonempty simultaneous push/pop, return the old top and replace it with wdata.
On an empty simultaneous push/pop, report underflow but still accept the push.
Compare rdata only for successful pops and check flags and depth every operation.