Hardware interview practice

Build a LIFO scoreboard

EasyVerificationSystemVerilog

Model and check a depth-8, 16-bit stack, including simultaneous push/pop, overflow, underflow, and reset behavior.

Starting point

Question code

// Sample after each rising edge:
{rst_n, push, pop, wdata, rdata, overflow, underflow}

Reviewed example

Input

Model contains [A,B] with B on top; push=C and pop=1 in the same cycle

Expected output

rdata=B, no error, model becomes [A,C]

The old top is returned before the simultaneous push replaces it.

What to cover

Use a depth-8 reference stack and clear it on reset.
On a nonempty simultaneous push/pop, return the old top and replace it with wdata.
On an empty simultaneous push/pop, report underflow but still accept the push.
Compare rdata only for successful pops and check flags and depth every operation.

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