1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ176

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Q176DVArchASIC interview problem

Model sparse banked memory with packed keys

TechniquesDVSystemVerilogAssociative arraySparse memoryReference model

DifficultyMedium

TopicReference Models

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Build a sparse SystemVerilog memory model addressed by an 8-bit bank and a 16-bit byte offset. Reads must distinguish an unwritten location from a location explicitly written with zero.

Type declarationSystemVerilog

typedef struct packed {
  bit [7:0]  bank;
  bit [15:0] offset;
} addr_t;

bit [31:0] mem[addr_t];

Example input and output

Use this case to check your interpretation

Input

write address '{bank:8'h02, offset:16'h0010} with 32'h0000_CAFE, then read the same address

Output

data = 32'h0000_CAFE, uninitialized_read = 0

Explanation

The packed struct forms one stable integral key, so the later lookup finds exactly the previously written bank-and-offset pair.

Requirements (4)

Store every valid write at the exact packed address key.
Check exists() before indexing on a read.
Return zero and assert uninitialized_read for an unwritten address.
Delete all associative-array entries on reset or model flush.