DescriptionQ318
Q318DVASIC interview problem
Verify a bounded step-sequence counter
TechniquesDVDynamic programmingLatencyResetScoreboard
DifficultyMedium
TopicReference Models
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Verify a single-request block that counts ordered sequences of one-step and two-step advances for distances from zero through 24.
Starting declarationSystemVerilog
logic clk, rst_n, start;
logic [4:0] steps;
logic busy, done, request_error;
logic [31:0] ways;
parameter int MAX_LATENCY = 28;Example input and output
Use this case to check your interpretationInput
request steps=5; then request steps=25Output
steps 5: ways=8,error=0; steps 25: ways=0,error=1Explanation
The legal request follows ways(5)=8, while 25 is above the supported bound and returns the defined zeroed error result.
02
Requirements (4)
- Predict ways(0)=1, ways(1)=1, and ways(n)=ways(n-1)+ways(n-2).
- Return request_error with ways zero for values above 24.
- Snapshot steps on acceptance and require one done pulse within the bounded latency.
- Ignore busy-time starts and cancel all pending completion obligations on reset.