DescriptionQ046
Q046DVASIC interview problem
FIFO Count Changes on Simultaneous Push and Pop
TechniquesDVWaveform DebuggingFIFO
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01
Problem
The FIFO is neither full nor empty. push and pop are accepted whenever asserted. count is the occupancy after each edge. Rule to apply: One accepted push adds one entry, one accepted pop removes one entry, and simultaneous accepted push and pop leave count unchanged. What causes the count mismatch at C3?
02