DescriptionQ014
Q014DVASIC interview problem
Read Attempt on an Empty FIFO
TechniquesDVWaveform DebuggingFIFO
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01
Problem
At each edge, pop and empty are sampled before the operation. occupancy is the number of stored entries immediately after the edge. Rule to apply: A pop is legal only when empty is 0. A pop while empty is 1 is an underflow attempt. What causes the error at C3?
02
