DescriptionQ911
Q911DVGoogleASIC interview problem
Assert ready-valid stability and response
TechniquesDVSystemVerilog assertionsReady-validLatency
DifficultyMedium
TopicAssertions and Formal
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
The producer must hold payload while stalled. At most one request may be outstanding, and each accepted request must observe rsp_valid at least once 1 to 4 cycles later. Reset cancels the obligation. Write two concurrent SVA properties for the interface.
Starting declarationSystemVerilog
logic clk, rst_n;
logic req_valid, req_ready;
logic [31:0] req_payload;
logic rsp_valid;
logic accept;
assign accept = req_valid && req_ready;Example input and output
Use this case to check your interpretationInput
accept at cycle 10; rsp_valid=1 only at cycle 13Output
The bounded-response property passes.Explanation
Cycle 13 is three clocks after acceptance and therefore lies inside the required 1-to-4-cycle window.
02
Requirements (4)
- Disable both properties while rst_n=0 using disable iff (!rst_n).
- If req_valid and not req_ready are sampled, require req_valid and req_payload to remain stable on the next cycle.
- Under the one-outstanding contract, every sampled accept requires rsp_valid on one of cycles 1 through 4.
- Use non-overlapping response timing so a response only in the acceptance cycle does not satisfy the requirement.