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Hardware interview practice

Assert ready-valid stability and response

MediumAssertions and FormalSystemVerilog

The producer must hold payload while stalled. At most one request may be outstanding, and each accepted request must observe rsp_valid at least once 1 to 4 cycles later. Reset cancels the obligation. Write two concurrent SVA properties for the interface.

Starting point

Question code

logic clk, rst_n;
logic req_valid, req_ready;
logic [31:0] req_payload;
logic rsp_valid;
logic accept;

assign accept = req_valid && req_ready;
Reviewed example

Work through one case

Input
accept at cycle 10; rsp_valid=1 only at cycle 13
Expected output
The bounded-response property passes.

Cycle 13 is three clocks after acceptance and therefore lies inside the required 1-to-4-cycle window.

What to cover

Requirements

  1. Disable both properties while rst_n=0 using disable iff (!rst_n).
  2. If req_valid and not req_ready are sampled, require req_valid and req_payload to remain stable on the next cycle.
  3. Under the one-outstanding contract, every sampled accept requires rsp_valid on one of cycles 1 through 4.
  4. Use non-overlapping response timing so a response only in the acceptance cycle does not satisfy the requirement.
Continue practicing
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